1. Field of the Invention
The invention relates generally to configurations and manufacturing methods of semiconductor power devices. More particularly, this invention relates to configurations and methods for manufacturing semiconductor power devices with a self-aligned process implemented with silicidation processes in recessed trenches to reduce required number of masks and further improve electrical contacts to the electrical terminals of the power device.
2. Description of the Prior Art
Even though power metal oxide semiconductor field effect transistors (MOSFETs) are well known in the semiconductor industry and there have been many patented disclosures and published technical papers related to trench MOSFET devices, e.g., trench FET, trench DMOS, etc., those who are involved in the fields of designing and manufacturing the power MOSFET devices are still confronted with technical difficulties and manufacturability limitations. Specifically, the manufacturing costs are increased when more masks are required to fabricate the power devices with complex configurations. The cost increase is even more severe with the advancement of technology when the structural features of the power device are further miniaturized. Furthermore, with shrunken dimension, the alignment tolerance of the power device is further tightened and that may often lead to reduced production yields and increased reliability issues and thus cause the production cost to increase. For these reasons, a technical challenge is now confronted for those of ordinary skill in the semiconductor industry to fabricate power device with smaller size, more precisely aligned structural features while reducing the number of masks to achieve cost savings.
In a US Patent Application (US 2009/0020810), Marchant discloses a trench MOSFET device manufactured with reduced mask requirements by applying a chemical mechanical planarization (CMP) method. FIG. 1A shows a cross sectional view of the device. However such device requires an extra mask to be used for the gate runner trench, and in the case of a shielded gate trench, another additional mask is needed for a shield runner electrode.
Tsui discloses in another U.S. Pat. No. 6,489,204, a trench MOSFET device formed by first using a hard mask thin SiO2 and Si3N4 films 14 and 15 respectively to etch a trench, and later to angle implant a source region 51 along the upper sidewalls of the trench, using the polysilicon plug 21 and SiO2 and Si3N4 films 14 and 15 as masks, as shown in FIG. 1B-1. As shown in FIG. 1B-2, SiO2 and Si3N4 films 14 and 15 are removed, dielectric spacers 71 are formed along the sidewalls of the trench above the polysilicon plug 22, and P+ body contact region 81 is implanted. In FIG. 1B-3, silicide contacts 91 are formed on the source and body regions 51, 81, and on the (gate) polysilicon plug 22. However, this method can result in the formation of gate to source electrical shorts due to the source body silicide and the gate silicide being formed at the same time. The spacers may not be enough to prevent bridges and leakage paths to form between the gate silicide and the source/body silicide. In addition, this invention does not disclose how to form a shield gate trench MOSFET, which is a more complex device requiring additional steps and considerations.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new device configurations and manufacturing method in forming the power devices such that the above discussed problems and limitations can be resolved.